1. Technical Field
This invention relates generally to electronic devices, and more particularly, to resistive memory devices.
2. Background Art
FIG. 1 illustrates a metal-insulator-metal (MIM) memory device 30. The memory device 30 includes an electrode 32 (for example copper), an insulating layer 34 (for example Ta2O5) on the electrode 32, and an electrode 36 (for example titanium) on the insulating layer 34. Initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 32, while a positive voltage is applied to electrode 36, so that an electrical potential Vpg is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This causes the overall memory device 30 to adopt a conductive, low-resistance (programmed) state (A, FIG. 2). Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an on-state resistance illustrated at B.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device 30, a positive voltage is applied to the electrode 32, while the electrode 36 is held at ground, so that an electrical potential Ver is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36. Application of this electrical potential causes the overall memory device 30 to adopt a high-resistance (erased) state illustrated at C.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the layer 34 (and memory device 30) in a high-resistance or substantially non-conductive state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
It will be understood that a memory device of this general type should be capable of use in a variety of conditions. For example, different device programming and erasing thresholds and on-resistance characteristics may be needed in different applications. Meanwhile, such a memory device should have rapid switching speed and show high stability in its programmed and erased states.
Therefore, what is needed is an approach wherein a memory device of the general type described above may be readily configured so as to be usable in a variety of conditions, meanwhile exhibiting rapid switching speed and high data storage stability.